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MATRA MHS
M 67025
8 K x 16 CMOS Dual Port RAM
Introduction
The M 67025 is a very low power CMOS dual port static RAM organised as 8192 x 16. The M 67025 is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or more width systems. The MATRA-MHS MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need of an additional discrete logic. Master and slave devices provide two independant ports with separate control, address and I/O pins that permit independant, asynchronous access for reads and writes to any location in the memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port in order to enter a very low stand by power mode. Using an array of eigh transistors (8T) memory cell and fabricated with the state of the art 0.65 lithography named SCMOS, the M 67025 combines an extremely low standby supply current (typ = 1.0 A) with a fast access time at 20 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 5 W. For military/space applications that demand superior levels of performance and reliability the M 67025 is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D Fast access time : 20/25/30/35/45/55 ns D Wide temperature range : -55 C to +125 C D 67025 L low power 67025 V very low power D Separate upper byte and lower byte control for multiplexed bus compatibility D Expandable data bus to 32 bits or more using master/slave chip select when using more than one device D On chip arbitration logic D Versatile pin select for master or slave : - M/S = H for busy output flag on master - M/S = L for busy input flag on slave D INT flag for port to port communication D Full hardware support of semaphore signaling between ports D Fully asynchronous operation from either port D Battery back-up operation : 2 V data retention D TTL compatible D Single 5 V 10 % power supply D For 3.3 V version, please consult sales
Rev. D (29/09/95)
1
M 67025
Interface
Block Diagram
MATRA MHS
Note :
1. (MASTER) : BUSY is output. (SLAVE) : BUSY is input. 2. LB = Lower Byte UB = Upper Byte
Pin Names
LEFT PORT
CSL R/WL OEL A0L - 12L I/O0L - 15L SEML UBL LBL INTL BUSYL M/S Vcc GND
RIGHT PORT
CSR R/WR OER A0R - 12R I/O0R - 15R SEMR UBR LBR INTR BUSYR
NAMES
Chip select Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground
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Rev. D (29/09/95)
MATRA MHS
M 67025
Functional Description
Pin Configuration
Top View
Rev. D (29/09/95)
3
M 67025
Pin Configuration
SEML I/O 2L R/WL I/O 7L I/O 4L I/O 3L I/O 0L OE L I/O 6L I/O 5L GND I/O 1L A 9L A 8L Vcc INDEX A 10L CE L LB L N/C A 11L UB L
MATRA MHS
I/O8L I/O9L I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L Vcc GND I/O0R I/O1R I/O2R Vcc I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 1 63 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 67025 F-84-2 84-PIN MQFPF FLATPACK TOP VIEW 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
A7L A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R
21 43 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 I/O 9R I/O 10R UB R LB R N/C A11R CE R I/O 12R I/O 13R SEMR A 10R A 11L GND I/O 11R I/O 14R GND I/O 15R OER R/WR A 8R A 7R A 8L A 9R A 10L
OEL Vcc R/WL
SEML CE L
I/O 2L
I/O 9L
I/O 7L
I/O 4L I/O 3L
I/O 0L
I/O 8L
I/O 6L
I/O 5L
GND I/O 1L
N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L Vcc GND I/O0R I/O1R I/O2R Vcc I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O 10R I/O 11R GND SEMR I/O 12R LB R A 12R CE R UB R GND I/O 15R A10R OE R A11R I/O 8R I/O 13R I/O 14R I/O 9R R/WR A 8R A 7R A 6R A 5R A 9R 67025 100-PIN TQFP TOP VIEW 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A 6L
A 9L
A 7L
INDEX
UB L LB L A12L
N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C
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I/O 7R
Rev. D (29/09/95)
MATRA MHS
M 67025
if the CSs are low before an address match, on-chip control logic arbitrates between the left and right addresses for access (refer to table 4). The inhibited port's BUSY flag is set and will reset when the port granted access completes its operation in both arbitration modes.
Functional Description
The M 67025 has two ports with separate control, address and I/0 pins that permit independent read/write access to any memory location. These devices have an automatic power-down feature controlled by CS.CS controls on-chip power-down circuitry which causes the port concerned to go into stand-by mode when not selected (CS high). When a port is selected access to the full memory array is permitted. Each port has its own Output Enable control (OE). In read mode, the port's OE turns the Output drivers on when set LOW. Non-conflicting READ/WRITE conditions are illustrated in table 1. The interrupt flag (INT) allows communication between ports or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location 1FFE (HEX). The left port clears the interrupt by reading address location 1FFE. Similarly, the right port interrupt flag (INTR) is set when the left port writes to memory location 1FFF (HEX), and the right port must read memory location 1FFF in order to clear the interrupt flag (INTR). The 16 bit message at 1FFE or 1FFF is user-defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not reserved for mail boxes but become part of the RAM. See table 3 for the interrupt function.
Data Bus Width Expansion Master/Slave Description
Expanding the data bus width to 32 or more bits in a dual-port RAM system means that several chips may be active simultaneously. If every chips has a hardware arbitrator, and the addresses for each arrive at the same time one chip may activate in L BUSY signal while another activates its R BUSY signal. Both sides are now busy and the CPUs will wait indefinitely for their port to become free. To overcome this "Busy Lock-Out" problem, MHS has developped a MASTER/SLAVE system which uses a single hardware arbitrator located on the MASTER. The SLAVE has BUSY inputs which allow direct interface to the MASTER with no external components, giving a speed advantage over other systems. When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a conflict situation. Conversely, the write pulse must extend a hold time beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is inherent in all dual-port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE must be inhibited by the MASTER's maximum arbitration time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the MASTER's BUSY signal.
Arbitration Logic Functional Description
The arbitration logic will resolve an address match or a chip select match down to a minimum of 5 ns determine which port has access. In all cases, an active BUSY flag will be set for the inhibited port. The BUSY flags are required when both ports attempt to access the same location simultaneously. Should this conflict arise, on-chip arbitration logic will determine which port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that allow the processor to hold the operation with its associated address and data. It should be noted that the operation is invalid for the port for which BUSY is set LOW. The inhibited port will be given access when BUSY goes inactive. A conflict will occur when both left and right ports are active and the two addresses coincide. The on-chip arbitration determines access in these circumstances. Two modes of arbitration are provided : (1) if the addresses match and are valid before CS on-chip control logic arbitrates between CSL and CSR for access ; or (2)
Semaphore Logic Functional Description
The M 67025 is an extremely fast dual-port 4k x 16 CMOS static RAM with an additional locations dedicated to binary semaphore flags. These flags allow either of the processors on the left or right side of the dual-port RAM to claim priority over the other for functions defined by the system software. For example, the semaphore flag can be used by oner processor to inhibit the other from accessing a portion of the dual-port RAM or any other shared resource.
Rev. D (29/09/95)
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M 67025
The dual-port RAM has a fast access time, and the two ports are completely independent of each another. This means that the activity on the left port cannot slow the access time of the right port. The ports are identical in function to standard CMOS static RAMs and can be read from, or written to, at the same time with the only possible conflict arising from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to prevent conflicts in the non-semaphore segment of the dual-port RAM. The devices have an automatic power-down feature controlled by CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when not selected. This conditions is shown in table 1 where CS and SEM are both high. Systems best able to exploit the M 67025 are based around multiple processors or controllers and are typically very high-speed, software controlled or software-intensive systems. These systems can benefit from the performance enhancement offered by the M 67025 hardware semaphores, which provide a lock-out mechanism without the need for complex programming. Software handshaking between processors offers the maximum level of system flexibility by permitting shared resources to be allocated in varying configurations. The M 67025 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more usual methods of hardware arbitration is that neither processor ever incurs wait states. This can prove to be a considerable advantage in very high speed systems.
MATRA MHS
reading it. If the latch has been set the processor assumes control over the shared resource. If the latch has not been set, the left processor has established that the right processor had set the latch first, has the token and is using the shared resource. The left processor may then either repeatedly query the status of the semaphore, or abandon its request for the token and perform another operation whilst occasionally attempting to gain control of the token through a set and test operation. Once the right side has relinquished the token the left side will be able to take control of the shared resource. The semaphore flags are active low. A token is requested by writing a zero to a semaphore latch, and is relinquished again when the same side writes a one to the latch. The eight semaphore flags are located in a separate memory space from the dual-port RAM in the M 67025. The address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, OE and R/W) as normally used in accessing a standard static RAM. Each of the flags has a unique address accessed by either side through address pins A0-A2. None of the other address pins has any effect when accessing the semaphores. Only data pin D0 is used when writing to a semaphore. If a low level is written to an unused semaphore location, the flag will be set to zero on that side and to one on the other side (see table 5). The semaphore can now only be modified by the side showing the zero. Once a one is writen to this location from the same side, the flag will be set to one for both sides (unless a request is pending from the other side) and the semaphore can then be written to by either side. The effect the side writing a zero to a semaphore location has of locking out the other side is the reason for the use of semaphore logic in interprocessor communication. (A thorough discussion of the use of this feature follows below). A zero written to the semaphore location from the locked-out side will be stored in the semaphore request latch for that side until the semaphore is relinquished by the side having control. When a semaphore flag is read its value is distributed to all data bits so that a flag set at one reads as one in all data bits and a flag set at zero reads as all zeros. The read value is latched into the output register of one side when its semaphore select (SEM) and output enable (OE) signals go active. This prevents the semaphore changing state in the middle of a read cycle as a result of a write issued by the other side. Because of this latch, a repeated read of a semaphore flag in a test loop must cause either signal (SEM or OE) to go inactive, otherwise the output will never change.
How The Semaphore Flags Work
The semaphore logic is a set of eight latches independent of the dual-port RAM. These latches can be used to pass a flag or token, from one port to the other to indicate that a shared resource is in use. The semaphore provide the hardware context for the "Token Passing Allocation" method of use assignment. This method uses the state of a semaphore latch as a token indicating that a shared resource is in use. If the left processor needs to use a resource, it requests the token by setting the latch. The processor then verifies that the latch has been set by
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MATRA MHS
The semaphore must use a WRITE/READ sequence in order to ensure that no system level conflict will occur. A processor requests access to shared resources by attempting to write a zero to a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as a one, and the processor will detect this status in the subsequent read (see table 5). For example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource concerned. If a processor on the right side then attempts to write a zero to the same semaphore flag it will fail, as will be verified by a subsequent read returning a one from the semaphore location on the right side has a READ/WRITE sequence been used instead, system conflict problems could have occurred during the interval between the read and write cycles. It must be noted that a failed semaphore request needs to be followed by either repeated reads or by writing a one to the same location. The simple logic diagram for the semaphore flag in figure 2 illusrates the reason for this quite clearly. Two semaphore request latches feed into a semaphore flag. The first latch to send a zero to the semaphore flag will force its side of the semaphore flag low and other side high. This status will be maintained until a one is written to the same semaphore request latch. Sould a zero be written to the other side's semaphore request latch in the meantime, the semaphore flag will flip over to this second side as soon as a one is written to the first side's request latch. The second side's flag will now stay low until its semaphore request latch is changed to a one. Thus, clearly, if a semaphore flag is requested and the processor requesting it no longer requires access to the resource, the entire system can hang up until a one is written to the semaphore request latch concerned. Semaphore timing becomes critical when both sides request the same token by attempting to write a zero to it at the same time. Semaphore logic is specially conceived to resolve this problem. The logic ensures that only one side will receive the token if simultaneous requests are made. The first side to make a request will receive the token where request do not arrive at the same time. Where they do arrive at the same time, the logic will assign the token arbitrarily to one of the ports. It should be noted, however, that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, errors can be introduced if semaphores are misused or misinterpreted. Code integrity is of the utmost performance when semaphores are being used instead of slower, more restrictive hardware-intensive systems.
M 67025
Semaphore initialization is not automatic and must therefore be incorporated in the power up initialization procedures. Since any semaphore flag containing a zero must be reset to one, initialization should write a one to all request flags from both sides to ensure that they will be available when required.
Using Semaphores - Some Examples
Perhaps the simplest application of semaphores is their use as resource markers for the M 67025's dual-port RAM. If it is necessary to split the 8 k x 16 RAM into two 4 K x 16 blocks which are to be dedicated to serving either the left or right port at any one time. Semaphore 0 can be used to indicate which side is controlling the lower segment of memory and semaphore 1 can be defined as indicating the upper segment of memory. To take control of a resource, in this case the lower 4 k of a dual-port RAM, the left port processor would then write a zero into semaphore flag 0 and then read it back. If successful in taking the token (reading back a zero rather than a one), the left processor could then take control of the lower 4 k of RAM. If the right processor attempts to perform the same function to take control of the resource after the left processor has already done so, it will read back a one in response to the attempted write of a zero into semaphore 0. At this point the software may choose to attempt to gain control of the second 4 k segment of RAM by writing and then reading a zero in semaphore 1. If successful, it will lock out the left processor. Once the left side has completed its task it will write a one to semaphore 0 and may then attempt to access semaphore 1. If semaphore 1 is still occupied by the right side, the left side may abandon its semaphore request and perform other operations until it is able to write and then read a zero in semaphore 1. If the right processor performs the same operation with semaphore 0, this protocol would then allow the two processes to swap 4 k blocks of dual-port RAM between one another. The blocks do not have to be any particular size, and may even be of variable size depending on the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the dual-port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on each side, rather than having a common meaning as is described in the above example. Semaphores are a useful form of arbitration in systems such as disk interfaces where the CPU must be locked out of a segment of memory during a data transfer operation, and the I/0 device cannot tolerate any wait states. If
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M 67025
semaphores are used, both the CPU and the I/0 device can access assigned memory segments, without the need for wait states, once the two devices have determined which memory area is barred to the CPU. Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. On a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in complex data structures. Block arbitration is very important in this case, since one processor may be responsible for building and updating
MATRA MHS
a data structure whilst the other processor reads and interprets it. A major error condition may be created if the interpreting processor reads an incomplete data structure. Some sort of arbitration between the two different processors is therefore necessary. The building processor requests access to the block, locks it and is then able to enter the block to update the data structure. Once the update is completed the data structure may be released. This allows the interpreting processor, to return to read the complete data structure, thus ensuring a consistent data structure.
Truth Table
Table 1 : Non Contention Read/Write Control.
INPUTS (1) CS
H X L L L L L L X H X H X L L Note : X X
OUTPUTS LB
X H H L L H L L X X H X H X L
R/W
X X L L L H H H X H H
OE
X X X X X L L L H L L X X X X
UB
X H L H L L H L X X H X H L X
SEM
H H H H H H H H X L L L L L L
IO8-IO15
Hi-Z Hi-Z DATAIN Hi-Z DATAIN DATAOUT Hi-Z DATAOUT Hi-Z DATAOUT DATAOUT DATAIN DATAIN - -
I/O0-I/O7
Hi-Z Hi-Z Hi-Z DATAIN DATAIN Hi-Z DATAOUT DATAOUT Hi-Z DATAOUT DATAOUT DATAIN DATAIN - -
MODE
Deselected : Power Down Deselected : Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Sema. Flag Read Data in Sema. Flag Write DIN0 into Sema. Flag Write DIN0 into Sema. Flag Not Allowed Not Allowed
1. A0L - A12L A0R - A12R.
Table 2 : Arbitration Options.
OPTIONS
Busy Logic Master yg Busy Logic Slave yg Interrupt Logic p g Semaphore Logic* p g
INPUTS CS
L L L L L L H H
OUTPUTS M/S
H H L L X X H L
UB
X L X L X L X X
LB
L X L X L X X X
SEM
H H H H H H L L
BUSY
Output Signal Input Signal -
INT
-
- - Output Signal -
H Hi-Z
* Inputs Signals are for Semaphore Flags set and test (Write and Read) operations.
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MATRA MHS
Table 3 : Interrupt Flag (1, 4).
LEFT PORT R/WL
L X X X Notes : 1. 2. 3. 4.
M 67025
RIGHT PORT INTL
X X L(3) H(2)
CSL
L X X L
OEL
X X X L
AOL-A12L
1FFF X X 1FFE
R/WR
X X L X
CSR
X L L X
OER
X L X X
AOR-A12R
X 1FFF 1FFE X
INTR
L(2) H(3) X X
FUNCTION
Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
Assumes BUSYL = BUSYR = H. If BUSYL = L, then NC. If BUSYR = L, then NC. H = HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE.
Table 4 : Arbitration (2)
LEFT PORT CSL
H L H L
RIGHT PORT CSR
H H L L
FLAGS (1) FUNCTION BUSYL
H H H H
A0L - A12L
X Any X A0R - A12R
A0R - A12R
X X Any A0L - A12L
BUSYR
H H H H No Contention No Contention No Contention No Contention
ADDRESS ARBITRATION WITH CS LOW BEFORE ADDRESS MATCH L L L L LV5R RV5L Same Same L L L L LV5R RV5L Same Same H L H L L H L H L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS LL5R RL5L LW5R LW5R Notes : = A0R - A12R = A0R - A12R = A0R - A12R = A0R - A12R LL5R RL5L LW5R LW5R = A0L - A12L = A0L - A12L = A0L - A12L = A0L - A12L H L H L L H L H L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
1. INT Flags Don't Care. 2. X = DON'T CARE, L = LOW, H = HIGH. LV5R = Left Address Valid 5 ns before right address. RV5L = Right Address Valid 5 ns before left address. Same = Left and Right Addresses match within 5 ns of each other. LL5R = Left CS = LOW 5 ns before Right CS. RL5L = Right CS = LOW 5 ns before left CS. LW5R = Left and Right CS = LOW within 5 ns of each other.
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M 67025
Table 5 : Example Semaphore Procurement Sequence.
FUNCTION
No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Note :
MATRA MHS
D0 - D15 LEFT
1 0 0 1 1 0 1 1 1 0 1
D0 - D15 RIGHT
1 1 1 0 0 1 1 0 1 1 1
STATUS
Semaphore free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left Port has semaphore token Semaphore free
1. This table denotes a sequence of events for only one of the 8 semaphores on the M 67025.
Figure 1. M 67025 - Semaphore Logic.
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MATRA MHS
M 67025
* Notice Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extented periods may affect reliability.
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND) : . . . . . . . . . . . . . . . . . . . -0.3 V to 7.0 V Input or output voltage applied : . . . . . . . . . . . . . . . (GND - 0.3 V) to (VCC + 0.3 V) Storage temperature : . . . . . . . . . . . . . . . . . . . . . . -65 C to +150 C
OPERATING SUPPLY VOLTAGE
Military Industrial Commercial VCC = 5 V 10 % VCC = 5 V 10 % VCC = 5 V 10 %
OPERATING TEMPERATURE
- 55 C to + 125 C - 40 C to + 85 C 0 C to + 70 C
DC Parameters
67025-20 Parameter Description ii Version i COM only ICCSB ( ) (1) Standby supply current (Both ports TTL level inputs) t l li t) Standby supply current (Both ports CMOS level inputs) t l li t) Operating supply current (Both ports active) t ti ) Operating supply current (One port active - One port standby) t ti O t t db ) V L V L V L V L 10 40 400 4000 320 340 220 220 COM 10 40 400 4000 310 330 210 210 67025-25 IND MIL 10 50 500 5000 350 370 210 210 67025-30 COM 10 40 400 4000 280 300 200 200 IND MIL 10 50 500 5000 320 340 200 200 67025-35 COM 10 40 400 4000 270 290 190 190 IND MIL 10 50 500 5000 300 320 190 190 UNIT VALUE
mA mA A A mA mA mA mA
Max Max Max Max Max Max Max Max
ICCSB1 ( ) (2)
ICCOP (3) ()
ICCOP1 (4) ()
DC Parameters (Continued)
67025-45 Parameter ii Description i Version COM ICCSB ( ) (1) Standby supply current (Both (B th ports TTL level inputs) t l li t) Standby supply current (Both (B th ports CMOS level inputs) t l li t) Operating supply current (B th ports active) t ti ) (Both Operating supply current (One (O port active - One port standby) t ti O t t db ) 1. 2. 3. 4. V L V L V L V L 10 40 400 4000 260 260 180 180 IND MIL 10 50 500 5000 260 280 180 180 67025-55 COM 10 40 400 4000 230 230 160 160 IND MIL 10 50 500 5000 230 260 160 160 UNIT VALUE
mA mA A A mA mA mA mA
Max Max Max Max Max Max Max Max
ICCSB1 ( ) (2)
ICCOP (3) ()
ICCOP1 (4) ()
Notes :
CSL = CSR 2.2 V. CSL = CSR VCC - 0.2 V. Both ports active - Maximum frequency - Outputs open - OE = VIH. One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level Inputs - CSL = CSR 2.2 V.
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M 67025
PARAMETER
IL I/O VIL VIH VOL VOH C IN C OUT Notes : (6) (7) (7) (5) (6)
MATRA MHS
67025-20/-25/-30/ -35/-45/-55
10 0.8 2.2 0.4 2.4 5 7
DESCRIPTION
Input/Output leakage current Input low voltage Input high voltage Output low voltage (I/O0-I/O15) Output high voltage Input capacitance Output capacitance
UNIT
A V V V V pF pF
VALUE
Max Max Min Max Min Max Max
5. Vcc = 5.5 V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc. 6. VIH max = Vcc + 0.3 V, VIL min = -0.3 V or -1 V pulse width 50 ns. 7. Vcc min, IOL = 4 mA, IOH = -4 mA.
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention : 1 - Chip select (CS) must be held high during data retention ; within VCC to VCC - 0.2 V. 2 - CS must be kept between VCC - 0.2 V and 70 % of VCC during the power up and power down transitions. 3 - The RAM can begin operation > tRC after VCC reaches the minimum operating voltage (4.5 volts).
Timing
VERSION PARAMETER (max)
ICCDR ICCDR Notes : 8. CS = VCC, Vin = Gnd to VCC. 9. tRC = Read cycle time.
UNIT UNIT
A A
TEST CONDITIONS (9) V
@ VCCDR = 2 V @ VCCDR = 2 V Com Ind, Mil 20 200
L
200 400
12
Rev. D (29/09/95)
MATRA MHS Test Conditions (8) AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Figure 2. Output Load. : GND to 3.0 V : 5 ns : 1.5 V
M 67025
Output Reference Levels : 1.5 V Output Load : see figures 2, 3
Figure 3. Output Load (for tHZ, tLZ, tWZ, and tOW).
AC Electrical Characteristics over the Full Operating Temperature and Supply Voltage Range
READ CYCLE Symbol Symbol (4) (5)
TAVAVR tRC TAVQV TELQV TBLQV tAA tACS tABE
M 67025-20 PARAMETER
M 67025-25
M 67025-30
M 67025-35
M 67025-45
M 67025-55
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Read cycle time Address access time Chip Select access time (3) Byte enable access time (3) Output enable access time Output hold from address change Output low Z time (1, 2) Output high Z time (1, 2) Chip Select to power up time (2) Chip disable to power down time (2) SEM flag update pulse (OE or SEM) 20 - - - - 3 3 - 0 - 12 - 20 20 20 11 - - 15 - 50 - 25 - - - - 3 3 - 0 - 12 - 25 25 25 13 - - 15 - 50 - 30 - - - - 3 3 - 0 - 15 - 30 30 30 15 - - 15 - 50 - 35 - - - - 3 3 - 0 - 15 - 35 35 35 20 - - 15 - 50 - 45 - - - - 3 5 - 0 - 15 - 45 45 45 25 - - 20 - 50 - 55 - - - - 3 5 - 0 - 15 - 55 55 55 30 - - 25 - 50 -
UNI T
ns ns ns ns ns ns ns ns ns ns ns
TGLQV tAOE TAVQX TELQZ TEHQZ TPU TPD TSOP Notes : tOH tLZ tHZ tPU tPD tSOP 1. 2. 3. 4. 5.
Transition is measured 500 mV from low or high impedance voltage with load (figures 2 and 3). This parameters is guaranteed but not tested. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. Refer to table 1. STD symbol. ALT symbol.
Rev. D (29/09/95)
13
M 67025
Timing Waveform of Read Cycle n 1, Either Side (1, 2, 4)
MATRA MHS
Timing Waveform of Read Cycle n 2, Either Side (1, 3, 5)
Timing Waveform of Read Cycle n 3, Either Side (1, 3, 4, 5)
Notes :
1. 2. 3. 4. 5.
R/W is high for read cycles. Device is continuously enabled, CS = VIL, UB or LB = VIL. This waveform cannot be used for semaphore reads. Addresses valid prior to or coincident with CS transition low. OE = VIL. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL. Refer to table 1.
14
Rev. D (29/09/95)
MATRA MHS AC Electrical Characteristics over the Full Operating Temperature and Supply Voltage Range
WRITE CYCLE PARAMETER Symbol (4) Symbol (5)
Write cycle time Chip select to end of write (3) Address valid to end of write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to end of write Output high Z time (1, 2) Data hold time (4) Write enable to output in high Z (1, 2) Output active from end of write (1, 2, 4) SEM flag write to read time SEM flag contention window
M 67025
M 67025-20
M 67025-25
M 67025-30
M 67025-35
M 67025-45
M 67025-55
UNI T
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
20 15 15 0 15 0 13 - 0 - 0 10 10 - - - - - - - 15 - 15 - - - 25 20 20 0 20 0 15 - 0 - 0 10 10 - - - - - - - 15 - 15 - - - 30 25 25 0 25 0 20 - 0 - 0 10 10 - - - - - - - 15 - 15 - - - 35 30 30 0 30 0 25 - 0 - 0 10 10 - - - 15 - 15 - - - - 45 40 40 0 35 0 25 - 0 - 0 10 10 - - - - - - - 20 - 20 - - - 55 45 45 0 40 0 30 - 0 - 0 10 10 - - - - - - - 25 - 25 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns
TAVAVW tWC TELWH TAVWH TAVWL tSW tAW tAS
TWLWH tWP TWHAX TDVWH TGHQZ TWHDX TWLQZ TWHQX TSWRD TSPS tWR tDW tHZ tDH tWZ tOW tSWRD tSPS
Notes :
1. Transition is measured 500 mV from low or high impedance voltage with load (figures 2 and 3). 2. This parameters is guaranteed but not tested. 3. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. This condition must be valid for entire tSW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. STD symbol. 6. ALT symbol.
Rev. D (29/09/95)
15
M 67025
Timing Waveform of Write Cycle n 1, R/W Controlled Timing (1, 2, 3, 7)
MATRA MHS
Timing Waveform of Write Cycle n 2, CS Controlled Timing (1, 2, 3, 5)
Notes :
1. 2. 3. 4. 5. 6. 7. 8. 9.
R/W must be high during all address transitions. A write occurs during the overlap (tSW or tWP) of a low CS or SEM and a low R/W. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle. During this period, the I/O pins are in the output state, and input signals must not be applied. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. Transition is measured 500 mV from steady state with a 5pF load (including scope and jig).This parameter is sampled and not 100 % tested. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. To access RAM, CS = VIL. SEM = VIH. To access upper byte CS = VIL, UB = VIL, SEM = VIH. To access lower byte CS = VIL, LB = VIL, SEM = VIH.
16
Rev. D (29/09/95)
MATRA MHS AC Electrical Characteristics over the Full Operating Temperature and Supply Voltage Range
WRITE CYCLE PARAMETER M 67025-20 M 67025-25 M 67025-30 M 67025-35
M 67025
M 67025-45
M 67025-55
UNIT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
BUSY TIMING (For Master 67025 only) tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD BUSY Access time to address BUSY Disable time to address BUSY Access time to Chip Select BUSY Disable time to Chip Select Write Pulse to data Delay (1) Write data valid to read data delay (1) Arbitration priority set-up time (2) BUSY disable to valid data - - - - - - 5 - 20 15 15 13 45 35 - Note 3 - - - - - - 5 - 25 20 20 17 50 35 - Note 3 - - - - - - 5 - 30 25 25 20 55 40 - Note 3 - - - - - - 5 - 35 30 30 25 60 45 - Note 3 - - - - - - 5 - 35 30 30 25 70 55 - Note 3 - - - - - - 5 - 45 40 40 35 80 65 - Note 3 ns ns ns ns ns ns ns ns
BUSY TIMING (For Slave 67025 only) tWB tWH tWDD tDDD Write to BUSY input (4) Write hold after BUSY (5) Write pulse to data delay (6) Write data valid to read data delay (6) 0 15 - - - - 45 35 0 17 - - - - 50 35 0 20 - - - - 55 40 0 25 - - - - 60 45 0 25 - - - - 70 55 0 25 - - - - 80 65 ns ns ns ns
Notes :
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read with BUSY (For Master 67025 only). 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) ot tDDD - tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveforms of Read with Port-to-port delay (For Slave, 67025 only)".
Rev. D (29/09/95)
17
M 67025
Timing Waveform of Read with BUSY (2, 3, 4) (For Master 67025)
MATRA MHS
Notes :
1. 2. 3. 4.
To ensure that the earlier of the two port wins. Write cycle parameters should be adhered to, to ensure proper writing. Device is continuously enabled for both ports. OE = L for the reading port.
Timing Waveform of Write with Port-to-Port (1, 2, 3) (For Slave 67025 Only)
Notes :
1. Assume BUSY = H for the writing port, and OE = L for the reading port. 2. Write cycle parameters should be adhered to, to ensure proper writing. 3. Device is continuously enabled for both ports.
18
Rev. D (29/09/95)
MATRA MHS Timing Waveform of Write with BUSY (For Slave 67025)
M 67025
Timing Waveform of Contention Cycle n 1, CS Arbitration (For Master 67025 only)
Rev. D (29/09/95)
19
M 67025
Timing Waveform of Contention Cycle n 2, Address Valid Arbitration (For Master 67025 only) (1) Left Address Valid First :
MATRA MHS
Right Address Valid First :
Note :
1. CSL = CSR = VIL
AC Parameters
INTERRUPT TIMING SYMBOL
tAS tWR tINS tINR Address set-up time Write recovery time Interrupt set time Interrupt reset time
67025-20 PARAMETER
67025-25
67025-30
67025-35
67025-45
67025-55 UNIT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
0 0 - - - - 17 17 0 0 - - - - 20 20 0 0 - - - - 25 25 0 0 - - - - 30 30 0 0 - - - - 35 35 0 0 - - - - 40 40 ns ns ns ns
20
Rev. D (29/09/95)
MATRA MHS Waveform of Interrupt Timing (1)
M 67025
Notes :
1. 2. 3. 4.
All timing is the same for left and right ports. Port "A" may bei either the left or right port. Port "B" is the port opposite from "A". See Interrupt truth table. Timing depends on which enable signal is asserted last. Timing depends on which enable signal is de-asserted first.
32-bit Master/Slave Dual-Port Memory Systems
Notes :
1. No arbitration in M 67025 (SLAVE). BUSY-IN inhibits write in M 67025 SLAVE.
Rev. D (29/09/95)
21
M 67025
Timing Waveform of Semaphore Read after Write Timing, Either Side (1)
MATRA MHS
Note :
1. CS = VIH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Contention (1, 3, 4)
Notes :
1. 2. 3. 4.
DOR = DOL = VIL, CSR = CSL = VIH, semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. Either side "A" = left and side "B" = right, or side "A" = right and side "B" = left. This parameter is measured from the point where R/WA or SEMA goes high until R/WB or SEMB goes high. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guaranted which side will obtain the flag.
22
Rev. D (29/09/95)
MATRA MHS
M 67025
PACKAGE RT DEVICE 67025V SPEED 25 blank /883 = MHS standards = MIL-STD 883 Class B or S FLOW
Ordering Information
TEMPERATURE RANGE C M M = 5 V version L = 3.3 V version QR = 84 pins J CERQUAD 8R = 84 pins PIN GRID ARRAY SR = 84 pins PLCC 42 = 84 pins LCC 8K x 16 Dual Port RAM K2 = 84 pins MQFPF* RT = 100 pins VQFP C = Commercial I = Industrial M = Military S = Space * 50 mils pitch 0 -40 -55 -55 to to to to +70C +85C +125C +125C L V EL EV
20 ns 25 ns 30 ns 35 ns 45 ns 55 ns
= Low power = Very low power = Low power and rad tolerant = Very low power and rad tolerant
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. D (29/09/95)
23

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